Packaging of integrated electronic devices, such as integrated circuits (ICs), Micro-Electro-Mechanical Systems (MEMs), Optical ICs (OICs), and the like often entails a bumping process during which solder bumps or copper (Cu) bumps are applied to a substrate that is to be joined to another substrate as a mounting interface to the external world. For example, FIG. 1A illustrates a chip substrate 105 with bumps 101 applied over pads 104 through solder resist 106. In the case of a ball grid array (BGA) technique or the related solder grid array (SGA) technique, the bumps 101 may be predominantly of copper (Cu) or any conventional solder alloy, such as Sn—Ag—Cu (SAC). As further illustrated in FIG. 1B, the chip substrate 105 is attached with the bumps 101 contacting receptacle pads 114 on a second substrate 110, which may be another chip, a package substrate, or the like. The bumps 101 are then reflowed to form an assembly 100 having conductive first level interconnects (FLI) between the two substrates 105 and 110. The bumping process may be further utilized as a second level interconnect (SLI) with bumps 102 interconnecting the substrate 110 to the substrate 120, as might be done for mounting a package to a PCB, for example.
Problems with the interconnect technology illustrated by FIGS. 1A and 1B include solder joint reliability (SJR) failures and interlayer dielectric (ILD) cracking within one or more of the substrates due to high stress concentrations, for example due to mismatch in coefficient of thermal expansion (CTE) between the substrates 105, 110, and/or 120. Recent developments in bulk solder composition for FLI and SLI have achieved only marginal reductions in stress with stiffness of copper bumps remaining. Costly architectures therefore continue to be employed to reduce stress, for example with a plurality of non-critical to function (nCTF) joints disposed at particular locations across a bumped substrate face. Another problem with the interconnect technology illustrated by FIGS. 1A and 1B is further illustrated in FIG. 1C with a plan view of the bumped face of the chip substrate 105. As shown, conventionally all bumps 101 have approximately the same dimension and a same composition so that the interconnect is independent of the function and/or location of a particular joint.
FLI and SLI structures offering lower stress and/or the prospect of functional alloying are therefore advantageous, as are the technologies associated with fabrication of such structures.